cient Analyses and Models of VLSI and MCM Interconnects

In performance-driven interconnect design, delay estimators are used to determine both the topol-ogy and the layout of good routing trees. We address the class of moment-matching methods used to model distributed RLC interconnects with a small number of lumped segment models. We provide new non-uniform segment models which match the transfer function of a general interconnect line with source and load impedance up to second-degree terms. We also use this methodology to derive non-uniform lumped segment models for open-ended distributed RLC lines. Our approach can be used to derive compact, non-uniform equivalent circuits which match the distributed line transfer function to any given accuracy. We have evaluated our models through simulation of interconnect networks by modeling the interconnect lines with non-uniform lumped segments and using the two-pole methodology. Although we use the two-pole method to demonstrate the advantage of our models and to reduce the complexity of simulation, the new models can be used within RLC model libraries for other circuit simulators such as SPICE. Previous two-pole approaches using traditional lumped segment models have over 25% error when compared to SPICE even for small interconnect tree examples. On the other hand, using our models the response becomes very close to the SPICE-computed response and delay estimates. For a wide range of interconnect parameters the delay estimates are all within 8% of SPICE-computed delays. As routing trees become bigger and interconnection lines become longer, particularly in MCM design, our approach has advantages in both accuracy and simulation complexity. Finally, we show that computing the transfer function coeecients alone is enough to calculate the driving point admittance for interconnection trees. With this technique the two phase transfer function coeecient computation for interconnection trees in 26] can be reduced to \single phase", which reduces the computation time.